Core parameters

Channels and rates

32-channel single-ended DIO (SDR mode)

16-channel bidirectional (DDR mode, bi-directional sampling)

Maximum clock / sampling rate: 200 MHz

Data width: 1 bit per channel, 32 channels in parallel

Level and drive

Level range: 1.2 V ~ 3.3 V programmable

Resolution: 100 mV step

Drive capability: single-ended, 50 Ω load matching

Standard: LVCMOS, LVTTL compatible

Board-mounted memory (per channel)

64 Mbit / channel (8 MB)

Total memory: 2 Gbit (256 MB)

Usage: waveform generation / acquisition cache, script sequence

Synchronization and triggering

Reference clock: 100 MHz / 200 MHz internal PLL or external input

Trigger: Start/Pause/Reference/Advance/Stop, Script Trigger ×4

Synchronization: PXIe backplane trigger (PXI_TRIG<0…6>), RTSI, external SMA (PFI0)

Timing: Independent timing per bank, configurable tCO, setup / hold time Interface

Front panel:

SMA: CLK IN, CLK OUT, PFI0 (trigger / clock)

VHDCI: 32-channel DIO + auxiliary signals

PXIe backplane: trigger, clock, high-speed data

Physics and environment

Size: 3U PXIe single slot (approx. 160 × 100 mm)

Weight: approximately 0.52 kg

Temperature: 0 °C ~ 55 °C (operating), −20 °C ~ 70 °C (storage)

Key features

200 MHz high-speed DIO: digital protocol testing, high-speed serial / parallel interface verification

Generation + acquisition integration: 32 channels can simultaneously output and sample, closed-loop testing

Hardware comparison (Bit Error Test): real-time comparison of expected / actual data, bit error rate analysis

Scripted waveform sequence: complex timing automatic playback, suitable for state machines / communication protocol testing

Mixed-signal synchronization: synchronized with PXIe analog cards, oscilloscopes, source meters, building a complete ATE

Typical applications

Digital chip / IP verification: GPIO, LVCMOS, DDR, SPI, I²C, UART, etc. interface testing

High-speed digital communication: parallel buses, custom protocols, baseband signal testing

Bit Error Rate (BER) testing: hardware real-time comparison, high-speed digital link reliability verification

Embedded system testing: MCU/FPGA digital interface automated testing

Semiconductor ATE, military / aerospace electronic test systems

Order information

781012‑02: Standard version (default levels / timings)

781012‑03: High-level / high-drive custom version (commonly specified by customers)

Comparison of similar products (overview)

PXIe‑6547: 100 MHz, 32 channels, 32 Mbit/ch (one level lower)

PXIe‑6548: 200 MHz, 32 channels, 64 Mbit/ch (mainstream high-speed)

PXIe‑6570/71: More advanced, up to 1 GHz, for ultra-high-speed serial testing